Venkat m Vlsi verification engineer
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I completed VLSI design and verification training.I have done some industry oriented projects.
I am able to code design using verilog. And i can verify them using system verilog and UVM . I have good knowledge on protocols.I can develop various test benches for the designs.I am interested to share my knowledge.
I start my lectures starting from basics.i strongly believe that one should be good in basics,then only he/she can become perfect in their fields.I first try to analyze the candidate skills and basing on that i will prepare my teaching style.

Subjects

  • SystemVerilog Beginner-Expert

  • Uvm (Universal Verification Methodology) Beginner-Expert

  • Verilog HDL Beginner-Expert

Experience

No experience mentioned.

Education

  • B.TECH (Jul, 2013–May, 2017) from JNTU, KAKINADA

Fee details

    ₹500–1,000/hour (US$5.86–11.73/hour)

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