Swamy Digital electronics,verilog,system verilog,UVM
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1.diffrent way of teaching
2.share my knowledge with easy way of teaching with examples.
3.delivery 100% content what I know with effient manner
4.students can understand with my visual presentation
5.coding with analysis and how the code run, execute and moreover debugging
6.suffient practice examples i will teach.
7.real time basic projects explain and verification
8.i can explain difficult topics with more easy of explanation
9.some examples explain with charts and flow diagrams
10. I will teach how to think problem solving,
11.way of think of problems solving with outofbound
12.80/20 formula for coding with

Subjects

  • Verilog Beginner-Intermediate

  • SystemVerilog Beginner-Expert

  • Uvm (Universal Verification Methodology) Beginner-Intermediate

Experience

  • Design verification engineer (Apr, 2022–Present) at Unkonwn
    Verification engineer

Education

  • Btech (Jan, 2013–Jul, 2016) from Unkonwn

Fee details

    ₹400–1,500/hour (US$4.68–17.55/hour)

    Online

Reviews

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