Kagitapu Yagnavallika Sai Trainee engineer
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• Having 2 years of relevant experience in VLSI Physical Design.
• Experience in Physical Design using Synopsys ICC2.
• Well Known about ASIC design flow from Netlist to GDS-II.
• Worked with industry standard tool at TSMC 40nm, 6nm technology nodes
• Good knowledge on Floor Planning, Power Plan, Placement, CTS and Routing, STA and finding the issues and fixing.
• Basic knowledge on Low power design concepts
• Known with concepts awk, sed and grep .
• Good knowledge on Linux
• Knowledge in writing scripts using TCL.

Technical Skills:

• EDA TOOLS : Synopsys ICC2, Prime Time
• Operating Systems : UNIX, Windows
• Scripting Language : TCL.
• Domain : ASIC Physical Design flow, STA.

Academics:

• B. Tech (2017 -2021) from Hindustan Institute of science and technology, Chennai with an aggregate of 89%
• Intermediate MPC (2015-2017) from APRJC Vizianagaram with an aggregate of 96.7%
• Secondary School of Education (2015) from B.V.M high school Rajahmundry aggregate of 97%
• After pursued my B.tech in 2021, started preparing for GATE and cracked gate 2022 with AIR 5125

Professional Experience:

BLR labs Pvt.Ltd : April-2022 to Present

Project Summary:

 Project-1

Title : ARDENC0
Client : AMD, Bangalore, India
Duration : 6 months
Tech-node : 6nm
Tools used : PRIME TIME
Frequency : 1.14 GHz
Clock names : Lclk, Aclk

Responsibilities:
• Done STA in block level and supported for Full chip level .
• Did timing report analysis and forwarded those to ECO generation team
• In Linux shell we used grep for bottle neck violations and informed those things to Eco generation team
• Did timing analysis for different paths and Identified false paths

 Project-2

INTERNAL PROJECT :

Tools : ICC II
Technology Node : 40nm
INST Count : 160k
Macro Count : 12
Clocks : 6
Metal Layer : 8
Frequency : 400MHz
Responsibilities:
• Learned entire PnR flow in this project.
• I applied path grouping for critical paths which made the timing better.
• floorplan experiments to meet timing and congestion requirements at place stage.
• After route I have fixed DRV’s by increasing the drive strength of driver and added buffer on long net.
• Manually fixed setup and hold violation after route by swapping SVT to LVT or high VT to low VT.

Personal Profile:
Languages : English, Telugu.

Subjects

  • Electronics & Communication Engineering Intermediate

  • Digital Electronics and Analog Electronics Intermediate

  • Control System Analysis Intermediate

Experience

  • Trainee engineer (Aug, 2022–Mar, 2024) at Blr pvt LTD

Education

  • B.TECH (Jun, 2017–May, 2021) from Hindustan Institute of Technology and Science, Chennai

Fee details

    ₹100–500/hour (US$1.17–5.85/hour)

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