Vijesh V System Verilog, UVM, APB, AHP, AXI
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Currently working as a Verification Engineer. Have a work experience of 3 years. Expert in System Verilog, UVM and verification environment using System Verilog and UVM, also having in-depth understanding of AMBA bus protocols like APB, AHB and AXI. So, I can help you with more of application-based learning and also job oriented learning.
My teaching method includes PPT and live coding examples. by the end you will have a complete understanding of Design Verification, EDA tools(like online EDA tool and modelsim or questasim) and Gvim text editor.

Subjects

  • VLSI Beginner-Intermediate

  • SV (SystemVerilog) Beginner-Intermediate

  • Uvm (Universal Verification Methodology) Beginner-Intermediate

Experience

No experience mentioned.

Education

  • BE (Jul, 2018–Jul, 2021) from Mangalore Institute of Technology and engineering mangalore

Fee details

    ₹300–500/hour (US$3.54–5.90/hour)

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