Alex RTL
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I am currently a digital IC designer, graduated from China and Denmark. I can help you on RTL design and relative system design questions, like projects for design a controller or processor, assignments occurred on computer architecture and so on. In terms of theoretical questions, like static timing analysis which is a well known difficult understanding part, I have helped my pairs during the exam periods, hope I can also help you here.
Except digital design, I do have hands on programming experience with microcontroller and firmware in C language, so if you have issues with MCU and hardware feel free to reach me.
Language I am using: Systemverilog/Verilog/VHDL, C/C++, python

Subjects

  • Verilog HDL and VHDL Diploma-Doctorate/PhD

  • Digital design and Verilog HDL Diploma-Doctorate/PhD

  • SV (SystemVerilog) Bachelors/Undergraduate-Doctorate/PhD

  • C / C++ & Data Structures Bachelors/Undergraduate-Doctorate/PhD

  • RTL (Register-transfer level) Bachelors/Undergraduate-Doctorate/PhD

Experience

  • Digital designer (Jul, 2019–Present) at Oticon copenhagen
    RTL design for SOC

Education

  • Msc EE (Sep, 2017–Jun, 2019) from DTU copenhagen

Fee details

    kr.100/hour (US$14.58/hour)

    Remotely on time

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