Pratap Shanbhag Design Verification Engineer
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I work as a system validation engineer in Intel India Pvt Ltd.
i have hands on experience on Verilog, system Verilog, UVM, OVM, Perl,
i have well subject knowledge of Electronics and Communication Engg subjects, Karnataka SSLC Board subjects (Social Science, Math's), Diploma subjects related to ECE etc..

I prepare my owns notes that helps student to understand the concept well.
Explanations of any subject should be based on example wise not just theoretical this helps the students to understand the topic very well.

The students should not study/understand the subjects just for scoring good in exams. He/She should understand the value of the particular subject and how its used in real life.

Subjects

  • Verilog Intermediate-Expert

  • Social Science Expert

  • Digital system design Expert

  • Micrcontroller 8051 Expert

  • Digital design and Verilog HDL Expert

Experience

  • SYSTEM VALIDATION ENGINEER (Jun, 2019–Present) at Intel

Education

  • MTECH IN VLSI AND EMBEDDED SYSTEM (Jun, 2018–Jun, 2020) from PES University Bengaluru
  • BTECH IN ELECTRONICS AND COMMUNICATION (Aug, 2015–May, 2018) from Reva University, bangalore, india–scored 8.5 CGPA

Fee details

    ₹1,000–2,000/hour (US$11.79–23.58/hour)

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