Sushil kumar Fpga/RTL design engineer
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An RTL and FPGA design engineer having working in corporate in last 3 years.
Associated with various Projects related to digital design ASIC/FPGA.
HDL Languages known : Verilog,VHDL
Protocols like : I2C,SPI,UART, Amba Protocols APB,AHB,AXI protocol.
Projects done : MIPI Alliance version 3
Made Microarchitecture Design for master and slave IP
FPGA Project :- Joint tactical Networking Centre (Six IP Nodes)
Tools Known : Cadence Ncsim,Xilinx Vivado 2022.1,Cadence Genus,Cadence JasperGold CDC/LINT
Can Teach Synthesis and Static Timing analysis as in Proffessional point of view.
Any Assignments/Projects related to RTL Design can contact.

Greeting of the Day,
Best regards
Sushil kumar

Subjects

  • FPGA Design Beginner-Expert

  • ASIC (Application-specific integrated circuit) Beginner-Expert

  • Digital design and Verilog HDL Beginner-Expert

Experience

  • Senior RTL Design Engineer (May, 2021–Present) at Incise infotech pvt ltd, Noida
    All the RTL and FPGA IP/SOC Designs making to the Silicon making process working with Verification, Synthesis and STA Teams.

Education

  • B.Tech (May, 2017–Aug, 2021) from MSIT, GGSIPU NEW DELHI

Fee details

    ₹500–1,500/hour (US$5.90–17.69/hour)

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