Miji shyam Mohanan FPGA design engineer
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I have 4 years of industrial experience in FPGA design .
Currently working on VHDL projects. I have experience in Verilog language also. I am strong in Digital logic design. I can help you with your digital design assignments. I have been coding in VHDL and verilog from past 7 years. I have experience in working on Vivado and ISE tools. I have experience in analysis of various reports from vivado like synthesis and timing.
I am currently working on 5G PHY layer . Specifically on HighPHY layer. All kinds of digital design assignments are welcome.

Subjects

  • VHDL Beginner-Expert

  • Verilog Beginner-Intermediate

  • FPGA Design Beginner-Expert

Experience

  • Senior design engineer (Jan, 2019–Present) at VVDN Technologies, Kochi
    RTL design engineer

Education

  • M Tech (Aug, 2017–Jul, 2019) from M A College, Kothamangalam, Kerala

Fee details

    ₹500–3,000/hour (US$5.79–34.71/hour)

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