Rob Verilog, RTL, Digital Design, FPGA, ASIC
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I am an FPGA designer with 7+ years of experience in the Telecom industry leading projects by acting as the FPGA architect, with expertise in system modeling, RTL design, simulation, architecture, implementation, and integration.

Experience summary:
- Extensive experience in Verilog/SystemVerilog/VHDL design, synthesis, and timing closure for FPGA design
- High-speed serial interface design and integration
- In-depth technical knowledge of MIPS CPU microarchitecture
- In-depth working knowledge of IEEE 802.3 Ethernet physical layer
- Teaching experience in university and industry
- Expert in computers, set up and support of enterprise level networking

P.S. I am a technology and computer nerd, always following new technology trends

Subjects

  • FPGA Design Beginner-Expert

  • Verilog HDL Beginner-Expert

  • Digital Design Systems Beginner-Expert

Experience

  • Senior SoC design engineer (Dec, 2021–Present) at .
  • Senior FPGA Design Engineer (Sep, 2012–Jan, 2020) at Parman Co.

Education

  • Electrical Engineering (Sep, 2011–Jun, 2014) from Sharif University of Technology, Tehran

Fee details

    leu80/hour (US$16.88/hour)

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