Nepolean RTL DESIGN TRAINEE
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- Adaptive and attentive training skill to create good sound in programming knowledge to bring an inspiring and hands-on learning experience.
- Provide motivation and support for the students where excellence in education is the focal point.
- Extensive training and hands-on experience.
- Excited to provide an inspiring learning experience to students.
- Ability to support individual learners with special educational needs.
- Skilled in adopting to students diverse learning styles and dynamic teaching method to reach unique needs
- Friendly relation with students.
- Highly Motivated and dedicated educator, wants all to be successful.

Subjects

  • SystemVerilog Beginner-Expert

  • Verilog HDL Beginner-Intermediate

Experience

  • RTL Design Trainer (Nov, 2020–Present) at Tessolve semiconductor
    Design and verification Trainer
  • RTL Design Trainer (Sep, 2019–Nov, 2020) at Test and verification solutions pvt Ltd Bangalore
    RTL Design Trainer
  • Assistant Professor (Jun, 2016–Mar, 2019) at K. S Rangasamy college of Engineering
    Teaching staff

Education

  • Master of Engineering (Jun, 2014–Apr, 2016) from K. S. Rangasamy College of Technology - Tiruchengode–scored 79%
  • Bachelor of Engineering (Aug, 2011–Apr, 2014) from Anna University trichy–scored 72%
  • Diploma (Jul, 2008–Apr, 2011) from Muthayammal Polytechnic College Rasipuram–scored 96%

Fee details

    ₹250–800/hour (US$2.95–9.43/hour)

    Vary with nature of task

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