Standard cell design and characterization tutors in Sector 11 Dwarka

  • Shyam G VLSI Engineer, Expert in Verilog,VHDL, Digital ele
Shyam G image

Good understanding of the ASIC design flow.
 Good knowledge in Digital Electronics, CMOS Technologies &
Static Timing Analysis
 Good knowledge in Hardware Descriptive language ie. Verilog
HDL, VHDL
 Experience in Development of IP level Verification platform using
System Verilog and UVM.
 Good knowledge in verification methodologies
...

  • Lado Sarai
  • ₹1,000–5,000/hour
  • 2.0 yr.
  • 2.0 yr.

Locations

Online